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Freescale Semiconductor Technical Data
Document Number: MPC17511A Rev 2.0, 4/2007
1.0 A 6.8 V H-Bridge Motor Driver IC
The 17511A is a monolithic H-Bridge designed to be used in portable electronic applications to control small DC motors or bipolar step motors. End applications include head positioners (CDROM or disk drive), camera focus motors, and camera shutter solenoids. The 17511A can operate efficiently with supply voltages as low as 2.0 V to as high as 6.8 V. Its low RDS(ON) H-Bridge output MOSFETs (0.46 typical) can provide continuos motor drive currents of 1.0 A and handle peak currents up to 3.0 A. It is easily interfaced to lowcost MCUs via parallel 3.0 V- or 5.0 V- compatible logic. The device can be pulse width modulated (PWM-ed) at up to 200 kHz. This device contains an integrated charge pump and level shifter (for gate drive voltages), integrated shoot-through current protection (cross-conduction suppression logic and timing), and undervoltage detection and shutdown circuitry. The 17511A has four operating modes: Forward, Reverse, Brake, and Tri-Stated (High Impedance). Features * 2.0 V to 6.8 V Continuous Operation * Output Current 1.0 A (DC), 3.0 A (Peak) * MOSFETs < 600 m RDS(ON) @ 25C Guaranteed * 3.0 V/ 5.0 V TTL- / CMOS-Compatible Inputs * PWM Frequencies up to 200 kHz * Undervoltage Shutdown * Cross-Conduction Suppression * Low Power Consumption * Pb-Free Packaging Designated by Suffix Codes EV and EP
17511A
H-BRIDGE MOTOR DRIVER IC
EV SUFFIX (PB-FREE) 98ASH70109A 16-PIN VMFP
EP SUFFIX (PB-FREE) 98ARL10577D 24-PIN QFN
ORDERING INFORMATION
Device MPC17511AEV/EL -20C to 65C MPC17511AEP/ R2 24 QFN Temperature Range (TA) Package 16 VMFP
5.0 V
15 V 17511A VDD VM C1L GOUT C1H C2L C2H CRES OUT1 EN GIN IN1 IN2
MOTOR
MCU
OUT2 GND
Figure 1. 17511A Simplified Application Diagram
Freescale Semiconductor, Inc. reserves the right to change the detail specifications, as may be required, to permit improvements in the design of its products.
(c) Freescale Semiconductor, Inc., 2007. All rights reserved.
INTERNAL BLOCK DIAGRAM
INTERNAL BLOCK DIAGRAM
C2L
Charge Pump
C2H
C1H
C1L
CRES GOUT
VDD
LowVoltage Shutdown VM
IN1
OUT1
IN2 VDD Control Logic
Level Shifter Predriver
OUT2
GIN VDD PGND
EN
LGND
Figure 2. 17511A Simplified Internal Block Diagram
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Analog Integrated Circuit Device Data Freescale Semiconductor
PIN CONNECTIONS
PIN CONNECTIONS
C2L C1H C1L VM VDD IN1 IN2 EN
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
C2H
CRES GOUT OUT2 PGND OUT1 GIN LGND
Figure 3. VMFP Pin Connections Table 1. VMFP Pin Function Description
Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Pin Name C2L C1H C1L VM VDD IN1 IN2 EN LGND GIN OUT1 PGND OUT2 GOUT CRES C2H Formal Name Charge Pump 2L Charge Pump 1H Charge Pump 1L Motor Drive Power Supply Logic Supply Input Control 1 Input Control 2 Enable Control Logic Ground Gate Driver Input H-Bridge Output 1 Power Ground H-Bridge Output 2 Gate Driver Output Charge Pump Output Capacitor Connection Charge Pump 2H Definition Charge pump bucket capacitor 2 (negative pole). Charge pump bucket capacitor 1 (positive pole). Charge pump bucket capacitor 1 (negative pole). Driver power supply voltage input pin. Control circuit power supply pin. Control signal input 1 Control signal input 2. Enable control signal input pin. Logic ground pin. LOW = True control signal for GOUT pin. Driver output 1 (right half of H-Bridge). Driver ground pin. Driver output 2 (left half of H-Bridge). Output gate driver signal to external MOSFET switch. Charge pump reservoir capacitor pin. Charge pump bucket capacitor 2 (positive pole).
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Analog Integrated Circuit Device Data Freescale Semiconductor
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PIN CONNECTIONS
24 23 22 21 20 19
VM VM VM VM NC NC
CRES
C1H
C2H
C1L
C2L
GOUT
1 2 3 4 5 6 7
VDD
18 17 16 15 14 13 8
IN1
NC OUT2 PGND PGND OUT1 NC
9 10 11 12
IN2 EN LGND GIN
Figure 4. QFN Pin Connections Table 2. QFN Pin Function Description
Pin Number 1, 2, 3, 4 5, 6, 13, 18 7 8 9 10 11 12 14 15, 16 17 19 20 21 22 23 24 Pin Name VM NC VDD IN1 IN2 EN LGND GIN OUT1 PGND OUT2 GOUT CRES C2H C2L C1H C1L Formal Name Motor Drive Power Supply No Connect Logic Supply Logic Input Control 1 Logic Input Control 2 Enable Control Logic Ground Gate Driver Input Output 1 Power Ground Output 2 Gate Driver Output Pre-Driver Power Supply Charge Pump 2H Charge Pump 2L Charge Pump 1H Charge Pump 1L Definition Driver power supply voltage input pin. This pin is not used. Control circuit power supply pin. Control signal input 1. Control signal input 2. Enable control signal input pin. Logic ground pin. LOW = True control signal for GOUT pin. Driver output 1 (right half of H-Bridge). Driver ground pin. Driver output 2 (left half of H-Bridge). Output gate driver signal to external MOSFET switch. Pre-driver circuit power supply pin. Charge pump bucket capacitor 2 (positive pole). Charge pump bucket capacitor 2 (negative pole). Charge pump bucket capacitor 1 (positive pole). Charge pump bucket capacitor 1 (negative pole).
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Analog Integrated Circuit Device Data Freescale Semiconductor
ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
Table 3. Maximum Ratings All voltages are with respect to ground unless otherwise noted. Exceeding the ratings may cause a malfunction or permanent damage to the device.
Rating Motor Supply Voltage Charge Pump Output Voltage Logic Supply Voltage Signal Input Voltage (EN, IN1, IN2, GIN) Driver Output Current Continuous Peak (1) ESD Voltage (2) Human Body Model Machine Model Storage Temperature Range Operating Ambient Temperature Operating Junction Temperature Thermal Resistance Power Dissipation
(3)
Symbol VM VCRES VDD VIN IO IOPK
Value -0.5 to 8.0 -0.5 to 14.0 -0.5 to 7.0 -0.5 to VDD + 0.5 1.0 3.0
Unit V V V V A
V VESD1 VESD2 TSTG TA TJ RJA PD
(5) (6), (7)
1800 100 -65 to 150 -20 to 65 -20 to 150 150 830 260 Note 7 C C C C/W mW C C
(4)
Soldering Temperature
TSOLDER TPPRT
Peak Package Reflow Temperature During Reflow
Notes 1. TA = 25C, 10 ms pulse width at 200 ms intervals. 2. 3. 4. 5. 6. 7. ESD1 testing is performed in accordance with the Human Body Model (CZAP = 100 pF, RZAP = 1500 ), ESD2 testing is performed in accordance with the Machine Model (CZAP = 200 pF, RZAP = 0 ). 37 x 50 x 1.6 [mm] glass EPOXY board mount. Maximum at TA = 25C. Soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device. Freescale's Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow Temperature and Moisture Sensitivity Levels (MSL), Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics.
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Analog Integrated Circuit Device Data Freescale Semiconductor
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ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 4. Static Electrical Characteristics Characteristics noted under conditions TA = 25C, VM = VDD = 5.0 V, GND = 0 V unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25C under nominal conditions unless otherwise noted.
Characteristic POWER Driver Circuit Power Supply Voltage Logic Supply Voltage Capacitor for Charge Pump Standby Power Supply Current Motor Supply Standby Current Logic Supply Standby Current Operating Power Supply Current Logic Supply Current (9) Charge Pump Circuit Supply Current Low VDD Detection Voltage (10) Driver Output ON Resistance (11) GATE DRIVE Gate Drive Voltage (12) No Current Load Gate Drive Ability (Internally Supplied) I CRES = -1.0 mA VC
(8)
Symbol
Min
Typ
Max
Unit
VM VDD C1, C2, C3 I I VMSTBY
2.0 2.7 0.01
5.0 5.0 0.1
6.8 5.7 1.0
V V F A mA
- -
- -
1.0 1.0
VDDSTBY I
VDD IC
- - 1.5 -
- - 2.0 0.46
3.0 0.7 2.5 0.60
mA mA V
RES
VDDDET RDS(ON)
VC VC
RES
V 12 13 13.5 V 10 11.2 - V
RESLOAD
Gate Drive Output IOUT = -50 A lIN = 50 A CONTROL LOGIC Logic Input Voltage Logic Input Function (2.7 V < VDD < 5.7 V) High-Level Input Voltage Low-Level Input Voltage High-Level Input Current Low-Level Input Current Pull-Up Resistance (EN, GIN) Notes 8. 9. 10. I I VDDSTBY includes current to the predriver circuit. VDD includes current to the predriver circuit. VIH VIL IIH IIL RPU VIN VGOUTHIGH VGOUTLOW
RES- 0.5
VC
RES- 0.1
VC
RES
LGND
LGND + 0.1 LGND + 0.5
0
-
VDD - VDD x 0.3 1.0 - 200
V
VDD x 0.7 - - -1.0 50
- - - - 100
V V A A k
Detection voltage is defined as when the output becomes high-impedance after VDD drops below the detection threshold. When the V V gate voltage CRES is applied from an external source, CRES = 7.5 V. IO = 1.0 A source + sink. Input logic signal not present.
11. 12.
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Analog Integrated Circuit Device Data Freescale Semiconductor
ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 5. Dynamic Electrical Characteristics Characteristics noted under conditions TA = 25C, VM = VDD = 5.0 V, GND = 0 V unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25C under nominal conditions unless otherwise noted.
Characteristic INPUT (EN, IN1, IN2, GIN) Pulse Input Frequency Input Pulse Rise Time Input Pulse Fall Time OUTPUT Propagation Delay Time Turn-ON Time Turn-OFF Time GOUT Propagation Delay Time Turn-ON Time Turn-OFF Time Charge Pump Circuit Rise Time
(17) (16) (13)
Symbol
Min
Typ
Max
Unit
fIN tR tF
- - -
- - -
200 1.0 1.0
(14) (14)
kHz s s
(15)
s
tPLH tPHL tSON tSOFF
tVCRESON
- -
0.55 0.55
1.0 1.0 s
- -
0.15 0.15
0.5 0.5 ms
-
0.1 -
3.0 10 ms
Low-Voltage Detection Time Notes 13. 14. 15. 16. 17.
t
VDDDET
-
Time is defined between 10% and 90%. That is, the input waveform slope must be steeper than this. Time is defined between 90% and 10%. When C1 = C2 = C3 = 0.1 F. Time to charge CRES to 11 V after application of VDD.
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Analog Integrated Circuit Device Data Freescale Semiconductor
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ELECTRICAL CHARACTERISTICS TIMING DIAGRAMS
TIMING DIAGRAMS
EN, IN1, IN2 (GIN)
VDDDETON
2.5 V/3.5 V 50%
VDDDETOFF
50%
tPLH (tSON)
OUT1, OUT2 (GOUT) 90% 10%
(tSOFF)
tPHL
VDD 0.8 V/ 1.5 V
t
VDDDET
t
90%
VDDDET
IM
0% (<1.0 A)
Figure 5. tPLH, tPHL, and tPZH Timing Table 6. Truth Table
INPUT EN H H H H L H H H = High. L = Low. Z = High impedance. X = Don't care. IN1 H H L L X X X IN2 H L H L X X X GIN X X X X X H L
Figure 6. Low-Voltage Detection
OUTPUT OUT1 L H L Z L X X OUT2 L L H Z L X X GOUT X X X X L L H
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Analog Integrated Circuit Device Data Freescale Semiconductor
FUNCTIONAL DESCRIPTION INTRODUCTION
FUNCTIONAL DESCRIPTION
INTRODUCTION
The 17511A is a monolithic H-Bridge power IC applicable to small DC motors used in portable electronics. The 17511A can operate efficiently with supply voltages as low as 2.0 V to as high as 6.8 V, and it can provide continuos motor drive currents of 1.0 A while handling peak currents up to 3.0 A. It is easily interfaced to low-cost MCUs via parallel 3.0 V- or 5.0 V-compatible logic. The device can be pulse width modulated (PWM-ed) at up to 200 kHz. The 17511A has four operating modes: Forward, Reverse, Brake, and Tri-State (High Impedance). Basic protection and operational features (direction, dynamic braking, PWM control of speed and torque, main power supply undervoltage detection and shutdown, logic power supply undervoltage detection and shutdown), in addition to the 1.0 A rms output current capability, make the 17511A a very attractive, cost-effective solution for controlling a broad range of small DC motors. In addition, a pair of 17511A devices can be used to control bipolar step motors. The 17511A can also be used to excite transformer primary windings with a switched square wave to produce secondary winding AC currents. As shown in Figure 2, 17511A Simplified Internal Block Diagram, page 2, the 17511A is a monolithic H-Bridge with built-in charge pump circuitry. For a DC motor to run, the input conditions need to be set as follows: ENable input logic HIGH, one INput logic LOW, and the other INput logic HIGH (to define output polarity). The 17511A can execute dynamic braking by setting both IN1 and IN2 logic HIGH, causing both low-side MOSFETs in the output H-Bridge to turn ON. Dynamic braking can also implemented by taking the ENable logic LOW. The output of the H-Bridge can be set to an opencircuit high-impedance (Z) condition by taking both IN1 and IN2 logic LOW. (refer to Table 6, Truth Table, page 8). The 17511A outputs are capable of providing a continuous DC load current of up to 1.2 A. An internal charge pump supports PWM frequencies to 200 kHz. The EN pin also controls the charge pump, turning it off when EN = LOW, thus allowing the 17511A to be placed in a power-conserving sleep mode.
FUNCTIONAL PIN DESCRIPTION OUT1 AND OUT2
The OUT1 and OUT2 pins provide the connection to the internal power MOSFET H-Bridge of the IC. A typical load connected between these pins would be a small DC motor. These outputs will connect to either VM or PGND, depending on the states of the control inputs (refer to Table 6, Truth Table, page 8). to the load attached between OUT1 and OUT2. All VM pins must be connected together on the printed circuit board with as short as possible traces offering as low impedance as possible between pins. VM has an undervoltage threshold. If the supply voltage drops below the undervoltage threshold, the output power stage switches to a tri-state condition. When the supply voltage returns to a level that is above the threshold, the power stage automatically resumes normal operation according to the established condition of the input pins.
PGND AND LGND
The power and logic ground pins (PGND and LGND) should be connected together with a very low-impedance connection.
IN1, IN2, AND EN
The IN1, IN2, and EN pins are input control pins used to control the outputs. These pins are 5.0 V CMOS-compatible inputs with hysteresis. The IN1, IN2, and EN work together to control OUT1 and OUT2 (refer to Table 6, Truth Table).
CRES
The CRES pin provides the connection for the external reservoir capacitor (output of the charge pump). Alternatively this pin can also be used as an input to supply gate-drive voltage from an external source via a series current-limiting resistor. The voltage at the CRES pin will be approximately three times the VDD voltage, as the internal charge pump utilizes a voltage tripler circuit. The VCRES voltage is used by the IC to supply gate drive for the internal power MOSFET H-Bridge.
GIN
The GIN input controls the GOUT pin. When GIN is set logic LOW, GOUT supplies a level-shifted high-side gate drive signal to an external MOSFET. When GIN is set logic HIGH, GOUT is set to GND potential.
C1L AND C1H, C2L AND C2H VM
The VM pins carry the main supply voltage and current into the power sections of the IC. This supply then becomes controlled and/or modulated by the IC as it delivers the power These two pairs of pins, the C1L and C1H and the C2L and C2H, connect to the external bucket capacitors required by the internal charge pump. The typical value for the bucket capacitors is 0.1 F.
17511A
Analog Integrated Circuit Device Data Freescale Semiconductor
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FUNCTIONAL DESCRIPTION FUNCTIONAL PIN DESCRIPTION
GOUT
The GOUT output pin provides a level-shifted, high-side gate drive signal to an external MOSFET with CISS up to 500 pF.
VDD
The VDD pin carries the 5.0 V supply voltage and current into the logic sections of the IC. VDD has an undervoltage
threshold. If the supply voltage drops below the undervoltage threshold, the output power stage switches to a tri-state condition. When the supply voltage returns to a level that is above the threshold, the power stage automatically resumes normal operation according to the established condition of the input pins.
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Analog Integrated Circuit Device Data Freescale Semiconductor
TYPICAL APPLICATIONS FUNCTIONAL PIN DESCRIPTION
TYPICAL APPLICATIONS
Figure 7 shows a typical application for the 17511A. When applying the gate voltage to the CRES pin from an external source, be sure to connect it via a resistor equal to, or greater than, RG = VCRES / 0.02 .
5.0 V 17511A
V
CRES < 14 V
RG > VCRES /0.02 RG
NC NC NC NC
0.01 F
C1L C1H C2L C2H CRES EN GIN IN1 IN2
VDD VM GOUT
OUT1
Motor Solenoid
OUT2
MCU
GND
NC = No Connect
Figure 7. 17511A Typical Application Diagram
CEMF SNUBBING TECHNIQUES
Care must be taken to protect the IC from potentially damaging CEMF spikes induced when commutating currents in inductive loads. Typical practice is to provide snubbing of voltage transients via placing a capacitor or zener at the supply pin (VM) (see Figure 8).
5.0 V 5.0 V 17511A VM VDD C1L C1H OUT1 C2L C2H CRES
OUT2
5.0 V 5.0 V 17511A VM VDD C1L C1H OUT1 C2L C2H CRES
OUT2
GND
GND
Figure 8. CEMF Snubbing Techniques
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Analog Integrated Circuit Device Data Freescale Semiconductor
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PACKAGING PACKAGE DIMENSIONS
PACKAGING
PACKAGE DIMENSIONS
For the most current package revision, visit www.freescale.com and perform a keyword search using the "98A" listed below.
EV (PB-FREE) SUFFIX 16-PIN VMFP PLASTIC PACKAGE 98ASH70109A ISSUE A
17511A
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Analog Integrated Circuit Device Data Freescale Semiconductor
PACKAGING PACKAGE DIMENSIONS
PACKAGE DIMENSIONS (CONTINUED)
EP (PB-FREE) SUFFIX 24-LEAD QFN NON-LEADED PACKAGE 98ARL10577D ISSUE A
17511A
Analog Integrated Circuit Device Data Freescale Semiconductor
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PACKAGING PACKAGE DIMENSIONS
PACKAGE DIMENSIONS (CONTINUED)
17511A
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Analog Integrated Circuit Device Data Freescale Semiconductor
REVISION HISTORY
REVISION HISTORY
REVISION 2.0
DATE 4/2007
DESCRIPTION OF CHANGES * * * Implemented Revision History page Converted to Freescale format Added Peak Package Reflow Temperature During Reflow (solder reflow) parameter and Note with instructions from www.freescale.com to Maximum Ratings Table 3
17511A
Analog Integrated Circuit Device Data Freescale Semiconductor
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MPC17511A Rev 2.0 4/2007

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